Testing of data communication devices and other electronic devices often involves waveform timing analysis in which it is necessary to record the exact time that an event in a waveform occurs. As the volume of data being transmitted through devices has been increasing, the speed of the signal waveforms that must be analyzed has also been increasing.
Typical time stamping circuitry counts the number of pulses received from a reference clock before an event in a waveform under test is detected. The time resolution of the counter method that is used in this type of time stamping circuitry is limited to the period of the reference clock and the maximum counting speed of the counter circuitry.
It has been known to extend time stamp resolution to less than one period of a reference clock by charging and discharging a capacitor with a reference clock and measuring the voltage of the capacitor at the time of an event. The time/discharge rate of the capacitor is generally known, so the time between a clock pulse and an event can be determined using knowledge of the capacitor voltage. However, this method suffers from some inaccuracy and requires calibration because the discharge rate of capacitors is generally non-linear and can differ significantly among capacitors.
Timing methods such as capacitive timing methods which use ramp waveforms are particularly susceptible to noise because ramp waveforms occupy a wide frequency band. This is especially true in a high density/multi-channel environment such as in test environments for digital devices. Increasing the slope of a ramp waveform can reduce noise but at the cost of higher current which increases power consumption and emissions, among other disadvantages.